Analog computing apparatus for performing square rooting, multiplication and logarithmic calculation

ABSTRACT

There is disclosed herein analogue computing apparatus comprising storage means so adapted that the value of a signal in the storage means may change as a function of time, an input to the storage means by means of which a first input signal may be applied to the storage means to determine a starting level for a stored signal therein, comparison means for comparing the stored signal with a second input signal, as the value of the stored signal changes with time, and providing a response when the compared signals have predetermined relationship, which will be after a time interval dependent (in a manner determined by the stored signal value/time characteristics of the storage means) on the first and second input signals, and converting means coupled to the comparison means and operable by said response to produce a signal related to the said time interval, which signal will thereby also be dependent on the first and second input signals.

United States Patent Richard Swarbrick;

George N. Nicolas Katselis, both of Honeywell Inc., Industrial ProductGroup, 1100 Virginia Drive, Fort Washington, Pa.

Inventors 19034 Appl. No. 866,980 Filed Oct. 16, 1969 Patented Jan. 11,1972 Priority Oct. 16, 1968 Great Britain 49,036/68 PrimaryExaminer-.I0seph F. Ruggiero I Attorneys-Arthur H. Swanson and LockwoodD. Burto ABSTRACT: There is disclosed herein analogue computingapparatus comprising storage means so adapted that the value of a signalin the storage means may change as a function of time, an input to thestorage means by means of which a first input signal may be applied tothe storage means to determine 4 Claims, 3 Drawing Figs. a startin levelfor a stored signal therein, com arison means 8 P U S Cl 235/193 forcomparing the stored signal with a second input signal, as 328/145 thevalue of the stored signal changes with time, and providing Int Cl G06g7/20 a response when the compared signals have predetermined 606g 7/24,relationship which win be am" a time interval dependent Field of Search235/193 a manner determined by the stored signal value/time charac- 194161 teristics of the storage means) on the first and second input 1 ,5 55 signals, and converting means coupled to the comparison means andoperable by said response to produce a signal related to the said timeinterval, which signal will thereby also be dependent on the first andsecond input signals.

STORAGE STORAGE 2 MEANS MEANS I 8 r i B o -1 1 13 1 J 102 IOU 1 L, 1

L J 9 i EQUAL/TY/ -7 G Z DETECTOR PATENTED JAN] 1 1972 SHEET 1 BF 3sromaas 2 MEANS T6 STORAGE MEANS 2 2 i EOUALITY/ 05 T56 rm ATTORNEY.

PATENTEU mu 1 I972 SHEET 2 UF 3 INVENTORS RICHARD SWARBRICK BY GEOEGENICOLAS KATSELIS m n H 1%). M FVv t TQM \mm W MN m A m 8 o q ull... WNmm 8 l QM 8w m 9 ,9 m9 m M 9 f? m l a 9 3 R w a m m m as -mv N E w 9& QT 8 Q m (w Q u VI. M W W cm Q mm ATTORNEY.

ANALOG COMPUTING APPARATUS FOR PERFORMING SQUARE ROOTING, MULTIPLICATIONAND LOGARITHMIC CALCULATION This invention relates to analogue computingapparatus.

Such apparatus is frequently required in systems, such as processcontrol systems, where the values of one or more variables (which maybe, for example, pressure or temperature), hereinafter referred to asdata values, are converted into signals whose values represent the datavalues, and computations have to be performed on one ore more of thesignals in order to derive a particular function which involves one ormore of the data values.

According to the present invention analogue computing apparatuscomprises storage means so adapted that the value of a signal in thestorage means may change as a function of time, an input to the storagemeans by means of which a first input signal may be applied to thestorage means to determine a starting level for a stored signal therein,comparison means for comparing the stored signal with a second inputsignal, as the value of the stored signal changes with time, andproviding a response when the compared signals have a predeterminedrelationship, which will be after a time interval dependent (in a mannerdetermined by the stored signal value/time characteristics of thestorage means) on the first and second input signals, and convertingmeans coupled to the comparison means and operable by said response toproduce a signal related to the said time interval, which signal willthereby also be dependent on the first and second input signals.

The converting means may comprise second storage means, so adapted thatthe value of a signal in the second storage means may change as afunction of time, and an input to the second storage means by means ofwhich a third input signal may be applied to the second storage means todetermine the starting level of a stored signal therein, the comparisonmeans being coupled to the second storage means and the second storagemeans being operable by said response of the comparison means toterminate the change of the stored signal therein, whereby the resultantsignal then in the second storage means will be dependent on all threeinput signals.

A preferred feature, which is incorporated in the particular embodimentdescribed in detail below, is that the first and second storage meansare such that their stored signals will change exponentially with time.

The first storage means may, however be such that its stored signal willchange linearly with time and the second storage means may be such thatits stored signal will charge exponentially with time, such anarrangement allowing computation of the antilogarithm of the data valuerepresented by the second input signal.

On the other hand, the first storage means may be such that its storedsignal will change exponentially with time and the second storage meansmay be such that its stored signal will change linearly with time, suchan arrangement allowing computation of the logarithm of the data valuerepresented by the second input signal.

Where both storage means have exponential characteristics, the apparatusmay also include:

(a) means for providing a first input signal having a predeterminedvalue. In this case the resultant signal will represent the function 6where F and E are data valneg represented by the second and third inputsignals respectively, and N is a number which is notnecessarily a wholenumber.

or (b) means for providing a third input signal having a predeterminedvalue. The resultant signal will represent the function where A is adata value represented by the first input signal. I

or (c) means for providing first and third input signals havingpredetermined values. The resultant signal will represent the functionor (d) means for providing first and second input signals havingpredetermined values. Resultant signal representing the function C. Themanner is which these functions arise in the output signal will beexplained in detail below.

N arises from having the time constant of the second storage means Ntimes that of the first storage means (N not necessarily being a wholenumber nor necessarily greater than one).

Conveniently, the predetermined relationship between the third inputsignal and the decaying signal in the first storage means is equality.

In a particular embodiment of the invention, which is described belowand which computes the square root of the second input signal, thissimple relationship allows the resultant signal automatically to beproduced on the same live zero" signal scale as the second input signal.A live zero scale is one where the lower limit of the input signal,which represents a data value of zero, is not zero but a finite value,and systems using such a scale are commonly preferred for thetransmission of analogue data signals. A scale commonly used is onewhere a current range of 4-20 milliamperes is used to represent the fullrange of data values from zero up to a selected maximum. In this scale,the current may be passed through a 250-ohm resistance to derive acorresponding 15 volt signal wherever a voltage signal may be requiredin the system.

The above distinction between data values (say E and E) and therespective signal values (which we may refer to as A B and C) by whichthey are represented, should be recognized. lt arises from the "livezero system, in which a portion of the actual signal value is not in anyway dependent on the data value but merely exists to bias the wholesignal scale away from zero.

In general, a scaling factor must be introduced in order toautomatically produce the resultant signal on the same live zero" scaleas the input signal or signals, where a live zero scale is being used,and in such a case preferably the said predetermined relationship issuch as to introduce a scaling factor required to produce a resultantsignal on the same signal scale as the variable input signal or signals.

In a particularly advantageous form of apparatus according to theinvention, the means for providing the input signal or signals having apredetermined value provide said signal or signals having a value equalto the upper limit value of a live zero" signal scale on which scale thevariable input signal or signals may represent data values, and theapparatus may comprise means for setting equal datum levels for thechanging stored signals in the two storagemeans, the datum levels havinga value equal to the lower limit value of said live zero" signal scale.

Alternatively, the means for providing the input signal or signalshaving a predetermined value provide said signal or signals having avalue equal to the upper limit value of a dead zero" signal scale onwhich scale the variable input signal or signals may represent datavalues, and the apparatus may comprise means for ensuring that the datumlevels for the changing stored signals in the two storage means arezero. A dead zero scale is one where a zero data value is actuallyrepresented by zero signal.

Preferably the apparatus is electrical apparatus, in which the first andsecond storage means each comprise capacitance, coupled to the storagemeans input so as to be able to receive an input signal therefrom, andalso resistance through which the capacitance may discharge therebychanging any voltage signal stored on it.

The comparison means may include two transistors in a long-tailed pairconfiguration.

In an embodiment described in detail hereinafter, a switching device isso connected into the resistance/capacitance circuit of the secondstorage means as to prevent or terminate decay of the voltage on thecapacitance when the switching device is rendered nonconductive.

The comparison means may be adapted to provide an output signal when thecompared signals have said predetermined relationship, and the apparatusmay comprise means for rendering the switching device associated withthe second storage means nonconductive in response to said outputsignal.

Preferably a switching device is similarly connected into theresistance/capacitance circuit of the first storage means.

The described embodiment also comprises respective input switching meansthrough which the respective storage means are connected to theirinputs, whereby the first and third input signals will be applied to therespective storage means when said input switching means are conductive.

A further feature which is preferably incorporated in apparatus inaccordance with the invention, in any of the forms referred to above, iscycling means for repeatedly a. applying the first and second inputsignals to the first and second storage means to set their startinglevels.

b. then initiating the change of the signals in both storage means, and

c. after termination of the change of the signal in the second storagemeans reapplying the first and second input signals to the first andsecond storage means to initiate another cycle.

This enables the function to be computed repetitively so that as thevariable input signal or signals varies the resultant signal isvirtually continuously varied also so as to continuously represent theappropriate function of the varying input signal or signals.

In the described embodiment, the cycling means comprises a two-statecircuit which is connected to the input switching means of both storagemeans and to the switching devices of both storage means in such mannerthat when in one state it provides signals to render the input switchingmeans nonconductive and the switching devices conductive, whereby thefirst and third input signals are not applied to the storage means whilethe signals in the latter decay, the two-state circuit having an inputconnected to the output of the comparison means whereby the outputsignal of the comparison means will place the two-state circuit in itsother state, wherein it provides output signals to render the inputswitching means conductive and the switching devices nonconductive, sothat the signals in the storage means are not able to decay while thefirst and third input signals are being applied to them to set theirstarting levels.

The two-state circuit may also be further provided with means fordelaying its response to the output signal of the comparison means.

Preferably also, gating means is provided for gating the said resultantsignal from the second storage means to an output of the apparatus, thegating means and the switching device of the second storage means beingconnected to respond immediately to the output signal from thecomparison means, whereby the delaying means of the two-state circuitallows the decay of the signal in the second storage means to beterminated and the resultant signal to be gated to the apparatus outputbefore the input switching means are rendered conductive.

In order that the invention may be more clearly understood, embodimentsin accordance with it will now be described, by way of example, withreference to the accompanying drawings, in which:

FIG. 1 is a block diagram of one form of computing apparatus inaccordance with the present invention,

FIG. 2 is a circuit diagram of a practical embodiment for continuouslycomputing a root or power function, and

FIG. 3 is a table which shows how a selection of other functions may becomputed.

It is convenient first to consider in general the requirements of anyform of analogue computipg apparatus which is to do a computation oftheform ,3

where 2, B and C are data values (for example, pressure or temperaturevalues) which are represented by respective signals having values A, Band C on a live zero" scale (and n 5 is not necessarily a whole numberand so may be a fraction),

and to produce an output signal representing the function on the samelive zero scale.

In general, take the upper and lower limits of the live zero" scale tobe 1 and 1,, respectively. The logical sequence of IO operations thenrequired in order to derive the required output signal is:

(a) Subtract I from each input signal-giving (A"IL); and (b) Take therequired function-giving (O-IL) (B40 (0) Multiply by a scaling factorKgiving K(CI ii-m IL) (d) Add I to the resultgiving r.) (BI-IL) which isa signal representing on the same live 40 zero scale.

We will revert to the above derivation after considering the apparatusshown in FIG. 1. Referring to FIG. 1, first and second storage means areshown at l and 2, respectively the storage means having respectiveinputs 3 and 4 by means of which input signals A and C can respectivelybe applied to them to set the storage means at starting levels A and Crespectively. The storage means are passive components and are soadapted that the value of a signal in either of them may change, fromits starting level, as a function of time. The changing signals, E and Eare provided on output connections 5 and 6.

Comparison means 7 is connected to the output connection 5 of the firststorage means 1 and also has an input 8 to which an input signal B isapplied. Comparison means 7 operates to compare the level of thechanging signal E in the first storage imeans l with the input signal B.The input signals A, C and B are respectively the first, third andsecond input signals hereinbefore referred to.

An operative coupling 9 is shown in broken lines, through which thecomparison means 7 operates to terminate the change of the signal E inthe second storage means 2 when the compared signals E, and B have apredetermined relationship. Most simply, this occurs when the comparedsignals are equal. The resultant signal E then present in the secondstorage means 2 will'then be dependent on all three input signals A, Band C, in a manner which will shortly be explained.

Preferably, as in the embodiment which will be described in detail withreference to FIG. 2, the storage means 1 and 2 have exponentialcharacteristics.

By the expression exponential characteristic," we mean a characteristichaving the general form E=(E,,a) e'/T+a where E is the value of thestored signal in the storage means at time t.

The changing stored signals in the two storage means at It can be seenfrom FIG. 3 that the apparatus will compute a signal representing, forexample, the product (col. 5 row 1), or quotient (col. 5 row 2) of twovariables. Referring to column 4, row 3, of FIG. 3, it can be seen thatwith a single variable if N l the Nth root is computed, or if N l theNth power is computed. In addition, of course, if all three inputs arevariable, and N is made equal to unity, the function where the suffixesl and 2 relate to the first and second storage means, respectively, andprovided of course that the changes are started simultaneously.

We can consider that T is equal to N T, (where N may be, but is notnecessarily, a whole number, and so could be a fraction). Assuming thatthe comparison means 7 terminates the change of the signal (E in thesecond storage means 2 when the signal (E,) in the first storage means 1is actually equal to the third input signal (C), then at that timeTaking the Nth root of the first of the above equations,

and eliminating e-lNT we have I 22 (xi-gr) (2) The similarity ofequations (1) and (2) should be noted. In fact, it can be seen that if,in the apparatus of FIG. 1, N is made equal to n of the requiredfunction, the datum levels a, and a are both made equal to the lowerscale limit I, and the signals A, B and C are applied to the apparatusas the first, second and third input signals, respectively only thefactor K remains to prevent the equations becoming identical. This maybe achieved by arranging the comparator so that, instead of producingits output signal when its two input signals (E and B) are equal, thisoccurs .when E,=K'(Ba,) +a,. This may be arranged by giving thecomparator an input circuit (as shown in broken lines in FIG. 1) whichcomprises a potentiometer 100 connected at one end to the B inputterminal and at the other to a terminal 101 held at the voltage a,, andan equality detecting circuit 102 which has one input connected toreceive the signal E, from the first storage means, and an other inputconnected to a slider 103 on the potentiometer. The slider position maythen be adjusted to produce the factor K' in the signal tapped off bythe slider.

With such an arrangement, correspondence has been established betweenthe resultant signal E and the ideal signal represented in equation (I),so that the apparatus will automatically compute a signal E, whichrepresents, on the same live zero" scale as the input signals, thefunction UXFE It has been assumed above that A, B and C are all variablesignals and that the output is to be a function of all of them. In fact,any one or two of these input signals may be made constant, so that theoutput signal will only vary with the remaining two, or one, of theinput signals. It can be shown that, in order to then preserve thedesirable feature of producing the output signal automatically on thesame live zero" scale as the input signals, it is necessary to set anyinput signals, which are to be constant, at a value ofh, the upper scalelimit.

FIG. 3 is a table which shows the form of the function computed when aselection of single ones of combinations of the input signals A, B and Care given the fixed value I,-. It is assumed, as before, that the inputsignals A, B, C, where they are not fixed, represent, on a live zerosystem, data values A, B and C respectively.

is computed.

It should here be mentioned that the apparatus described above withreference to FIG. 1 is subject to the limitation that A should begreater than B, so that the quotient computation (row 2 in FIG. 3),which involves variation of both A and B, will only be performedeffectively so long as A B. For the same reason, if B alone, or both Cand B, are fixed and the other(s) allowed to vary, operation on aconsistent live zero scale is precluded.

The above examples are among the most commonly required forms offunction, and the apparatus will (subject to the limitation referred toabove) compute signals which represent any one of them on the same livezero" scale as the input signals, provided the variable input signal orsignals is or are applied to the appropriate inputs, the fixed inputsignals are set at the value 1,, and the base levels are set at thevalue 1,

It will be apparent from the foregoing description that for a dead zerosystem, i.e., where a zero data value is actually represented by a zerovalue signal (that is to say I =0) the datum levels a, and a, may be setto zero. In that case the output signal E will have a simpler form, ascan be seen by setting I equal to Zero in the third column of FIG. 3,but the functions represented will still be as indicated in the fourthand fifth columns and will be on the same "dead zero" scale (0-! as theinput signals. With a,=0 the comparator should operate, in general, whenE,=KB. This can be achieved simply by having a comparator with an inputcircuit which multiplies B by K.

If, instead of setting any nonvariable input signal toa value I whichwas said to be necessary in order to produce an output signal on theright scale, they are set to a different constant value, then the effectis to produce an output signal which is on a scale related to, but notidentical with, the scale of the variable input signals.

Referring now to FIG. 2 of the drawings, which shows a circuit, inaccordance with the invention, which includes means for internallyproviding input signals A and C which have equal predetermined values,and for setting the datum levels also to equal predetermined values. Thecircuit thus performs the Nth root function, to which the third row ofFIG. 3 relates, and in fact the circuit components which determine thestorage means time constants have been chosen to make N equal 2, so asto compute the square root. The circuit is intended to operate in a 4-20milliamperes (or l-S volts) live zero system so the first and secondinput signals are set at 5 volts while the datum levels are set at 1volt.

In this particular instance, then N=2, I,=5 volts, and I =I volt.Substituting these values in the equation of the fourth row of FIG. 3gives 4K i;-1 i

It is known that when B=S volts, E must equal 5 volts. Substitutingthese values in the above equation, it is found that K must be unity.Consequently the comparator 7 can in this case merely be an equalitydetector, thus making K=l, yet the apparatus will still compute anoutput signal on the same live zero" scale as the input signal.

Now, relating FIG. 2 to FIG. 1, the first storage means 1 comprises acapacitor 10 in parallel with resistors 11, 12 and 13. The voltagesignal on capacitor 10 can decay when a transistor 0,, between resistors11 and 12, is conductive,

thereby allowing the capacitor 10 to discharge exponentially through theresistors.

The second storage means comprises a capacitor 14 in parallel withresistors 15, 16 and 17. A transistor 0,, is connected between resistors16 and 17 and, when conductive, allows the voltage on capacitor 14 todecay in a similar manner.

The input connections 3 and 4 to the respective storage means areconnected in common to a line 18 which derives a voltage from a tappedresistor 19 which is connected to the junction between a resistor 20 anda Zener diode 21. The latter two components are connected in seriesbetween power supply lines 22, 23 so that Zener diode 21 (whichnominally provides 6.6 volts) establishes a stable voltage from which avolt signal can be applied to connections 3 and 4 by suitably adjustingthe tapping on resistor 19. The 5 volt signals on connections 3 and 4are A and C respectively, so that these two input signals are internallyprovided in this instance. These signals are applied to the capacitorsand 14 of the respective storage means when transistors Q, and Qconnected into connections 3 and 4 respectively, are renderedconductive.

The comparator 7 comprises two transistors Q and Q connected as along-tailed pair in a generally known manner so as to form an equalitydetector. Input connection 8, to which the second, and variable, inputsignal 19 is to be applied, is connected to the base of 0,, while a line5 connects the base ofQ to the capacitor 10 in the first storage means.Hence Q will be cut off so long as E the voltage on capacitor 10, isgreater than B, but will conduct as soon as E decays to a level equal toB.

The remainder of the circuit can conveniently be described inconjunction with a description of one cycle of operation of the circuit.Since the operation is cyclic it is convenient to assume arbitrarily astarting point where both capacitors 10 and 14 have been charged totheir starting level of 5 volts. They then start to discharge(transistors Q and 0 being at this time conductive, while transistors Qand Q are nonconductive) at rates which depend on the time constants ofthe RC combinations mainly consisting of components 10, ll, 12, 13 and14, l5, l6, 17. The values of components 42, 43, 19, and 21 also have aneffect on these time constants which is very small owing to their verysmall values in relation to resistors 11 and 15. In this circuit, whichis intended to compute a square root function, N should be equal to 2,i.e., ifthe capacitors l0, 14 are equal, the total value of resistors15, 16 and 17 should be twice that of resistors 11 and 13 and theoperative portion of resistor 12. The capacitor values could, of course,be varied also, or instead, to obtain the desired value of N.

As soon as E,, the decaying voltage on capacitor 10, becomes equal to B,Q conducts, hence producing an output signal from the comparator acrossa resistor 24 in the collector circuit of Q This output signal isapplied to the base of transistor O in a switching circuit. Q thereforeconducts and its collector voltage drops to the negative supply voltageon line 23. This voltage drop is applied byline 25 through a diode 26 tothe base of 0 which immediately stops conducting thus terminating thedecay of the voltage on capacitor 14 of the second storage means. Thesame voltage drop is applied through a resistor 26a to the base of Q,and cuts it off so that a voltage rise occurs at the collector of 0,.This voltage rise is applied through a resistor 27, line 28 andcapacitor 29 to the base ofQ which then conducts to allow the resultantvoltage signal E on capacitor 14 to be provided on output connection 6.

Transistors Q and O in the switching circuit form the active elements oftwo-state circuit which has one state in which 0 is conductive and Q5nonconductive. However, the aforementioned voltage rise at the collectorof Q, is applied also through a resistor 30 to the base of 0 whichswitches the two-state circuit to its other state in which 0,, conductsand Q does not. because of the voltage drop then applied to the base of0,, through resistor 33. As Q, conducts, the line 28 is put back to thenegative supply voltage on line 23 by conduction the base ofQ by thevariable input signal equal to I (5 volts), and a, and a,

of a diode 34, so that conduction of Q is terminated. However, a delayoccurs between the initiation and termination of conduction of Q wing tothe provision ofa RC delay circuit which includes a capacitor 32 andalso the resistor 30, which delays the application of the voltage risethrough resistor 30 to This delay allows the output signal E to beprovided on connection 6 for a sufficient time for it to be transferredto an output capacitor 44 which will provide a continuous output voltagewhich will represent the desired function (in this case the square root)of the data value (3) represented As Q conducts, not only does it cutoff On, but it also applies a voltage drop through a line 35 andrespective resistors 36, 37 and 38 to the bases of Q Q and Q causing Qand Q to conduct, so that capacitors l0 and 14 start being charged up totheir starting level of 5 volts again, and causing 1 to becomenonconductive so that capacitor 10 cannot discharge through it.

Q, would be rendered conductive again as capacitor 14 charges to avoltage above B, since the comparator output would then cease. In orderto avoid this, which would prevent proper recharging of capacitor 14, aline 39 is connected from the collector of 0,, through a diode 40 to thebase of 0,. Thus, even when the comparator output ceases Q, will bemaintained in conduction by capacitor 32 for sufficient time to keep 0,,nonconductive throughout the full recharging of capacitor 14.

After capacitors l0 and 14 have recharged to 5 volts, in a timedetermined by capacitor 32 and resistors 45 and 31, Q, will revert toits normal nonconductive state, Q becoming conductive, and hence Q andQ10 will be rendered nonconductive, and Q rendered conductive, by theresultant positive signal on line 35, while 0,, will be renderedconductive by the resultant positive signal on line 39. Thus bothcapacitors start to discharge again, this being the beginning of thenext computing cycle. A resistor 46 is shown, which has a very highvalue and is intended to prevent buildup of charge on the gate Referringto the earlier part of this description, datum levels a and 0 were therereferred to. In the circuit of FIG. 2, the resistors l2 and 13 of thefirst storage means form part of a resistor chain 42, 12, 13 between the5-volt line 18 and the negative supply line 23. Similarly a resistor 43is connected in series with resistor 17 of the second storage means toform a chain between lines 18 and 23. The resistance values in thesechains are selected and adjusted so that the capacitor voltages cannotdecay below 1 volt. In this way the datum levels a and a are both madeequal to I the lower limit ofthe live zero" scale, as already discussedwith reference to FIG. 1.

It will be appreciated that the storage means in this particular circuithave been given exponential decay characteristics so related that N isequal to 2, A and C have both been made have both been made equal to (1volt). Referring to the third row of FIG. 3, it is evident that theresultant signal E provided intermittently at output connection 6 andacross capacitor 44, represents on the [-5 volt live zero" scale thesquare root of the data value represented by the third input signal Bapplied at input 8, if the l tt isalswnfihs 1:5. v .ivszer 1212..

Substantially the same circuitry as is shown in FIG. 2 may be used toderive any others of the functions shown in FIG. 3.

If, for instance, A or C are to be variable signals, the appropriatestorage means input connection 3 or 4 will be detached from the line 18and connected instead to a source of the variable voltage signal (A orB) which is to contribute to the output function. As this voltage signalvaries, so the capacitor in the respective storage means will becomecharged to slightly different starting levels in successive cycles ofoperation, and hence the variable voltage will have its effect on theoutput signal E in accordance with the above equations and the table ofFIG. 3.

If B is to be nonvariable (equal to 5 volts, for example, if

operating on the 1-5 volt scale) it will be connected to a constantvoltage source, such as line 18.

The datum levels of the storage means can be made equal to zero, foroperation on a dead zero scale, by having an open circuit in place ofresistors 42 and 43, so that no bias voltage will be applied to thecapacitors and 14.

it will be appreciated that a more complex form of constant voltagesupply may be provided if the accuracy of the circuit is required to begreater.

It can be seen from FIG. 3 that if N is made less than I, the power ofthe data values, instead of their roots, will appear in the outputfunction. For example, with N= /z, the arrangement referred to in thethird row of the table, which is the same arrangement as shown in detailin FIG. 2, will produce a signal representing the square of E It willnow be appreciated that in the apparatus described with reference toFIGS. 1 and 2, the first storage means and the comparison means act inconjunction to delineate a time interval which is dependent on both thefirst and second input signals A and B, and also on the stored signalvalue/time characteristics of the first storage means. The secondstorage means then operates to convert this time interval into an outputsignal which is related to the value of the time interval, and hence isalso dependent on A and B.

When the second storage means has an exponential stored signalvalue/time characteristic, as described, then it itself introduces afurther factor to the function computed. The second storage means may,however, to be given a linear characteristic, by providing aconstant-current discharge path for the storage capacitor 10.Constant-current arrangements are well known, and it is not considerednecessary to describe any in detail here.

The effect then is, assuming that the comparator gives its output signalwhen equality is detected and the datum level is set to zero, that thecomparator produces an output signal when -i B=A 1 so that It also thesecond storage means is arranged to start from the zero datum level andcharge towards, C, then E =k Ct, where k is a constant.

Consequently, when the change in E is terminated,

Thus in this form, assuming C and B are held constant the apparatus willcompute a voltage representing the natural logarithm of A. Here theconversion of time interval to output signal is done linearly. Otherlogarithms to any base can be computed by appropriate choice ofk and7",.

An antilogarithm computation may be done by giving the first storagemeans a linear characteristic and the second storage means anexponential one.

Then E,=AkAt (k' being a constant) so that when the change in E isterminated,

E C antilog Hence, keeping A and C constant, this arrangement willcompute a signal representing the natural antilogarithm ofBi Otherantilogarithms to any base can be computed by appropriate choice of kand T We claim:

1. Analog computing apparatus comprising storage means so adapted thatthe value of a signal in said storage means may change of the functionof time, said storage means having an input by means of which a firstinput signal may be applied to said storage means to determine astarting level for a stored signal therein, comparison means coupled tosaid storage means for comparing said storage signal with a second inputsignal, as the value of the said stored signal changes with time. andproviding a response when the compared signals have a predeterminedrelationship, which will be after a time interval dependent (ina matterdetermined by the stored signal value/time characteristics of saidstorage means) on said first and second input signals, and convertingmeans coupled to said comparison means and operable by said response toproduce a signal related to the said time interval, which signal willthereby also be dependent on said first and second input signals, saidconverting means including second storage means, so adapted that thevalue of a signal in said second storage means may change as a functionof time, and an input to said second storage means by means of which athird input signal may be applied to said second storage means todetermine the starting level of a stored signal therein, said comparisonmeans being coupled to said second storage means and said second storagemeans being operable by said response of said comparison means toterminate the change of the stored signal therein, whereby the resultantsignal then in said second storage means will be dependent on all threeinput signals, said first and second storage means are such that theirstored signals will change exponentially with time, means for providinga first input signal having a predetermined value, said predeterminedrelationship between said second input signal and the stored signal insaid first storage means is equality, said means for providing the inputsignal or signals having a predetermined value provide said signal orsignals having a value equal to the upper limit value of a live zero"signal scale on which scale the variable input signal or signals mayrepresent data values, and including means for setting equal datumlevels for the changing stored signals in the two storage means, thedatum levels having a value equal to the lower limit value of said livezero signal scale.

2. Analog computing apparatus comprising storage means so adapted thatthe value of a signal in said storage means may change of the functionof time, said storage means having an input by means of which a firstinput signal may be applied to said storage means to determine astarting level for a stored signal therein, comparison means coupled tosaid storage means for comparing said storage signal with a second inputsignal, as the value of the said stored signal changes with time, andproviding a response when the compared signals have a predeterminedrelationship, which will be after a time interval dependent (in a matterdetermined by the stored signal value/time characteristics of saidstorage means) on said first and second input signals, and convertingmeans coupled to said comparison means and operable by said response toproduce a signal related to the said time interval, which signal willthereby also be dependent on said first and second input signals, saidconverting means including second storage means, so adapted that thevalue of a signal in said second storage means may change as a functionof time, and an input to said second storage means by means of which athird input signal may be applied to said second storage means todetermine the starting level of a stored signal therein, said comparisonmeans being coupled to said second storage means and said second storagemeans being operable by said response of said comparison means toterminate the change of the stored signal therein, whereby the resultantsignal then in said second storage means will be dependent on all threeinput signals, said first and second storage means are such that theirstored signals will change exponentially with time, means for providinga first input signal having a predetermined value,

said predetermined relationship between said second input signal and thestored signal in said first storage means is equality, said means forproviding the input signal or signals having a predetermined valueprovides said signal or signals having a value equal to the upper limitvalue ofa dead zero" signal scale on which scale the variable inputsignal or signals may represent data values, and comprising means forensuring that the datum levels for the changing stored signals in thetwo storage means are zero.

3. Apparatus according to claim 1 including cycling means for repeatedlya. applying the first and second input signals respectively to the firstand second storage means to set their starting levels,

b. then initiating said change of the stored signals in both storagemeans, and

c. after termination of the change of the stored signal in the secondstorage means reapplying the first and second input signals respectivelyto the first and second storage means to initiate another cycle.

4. Apparatus according to claim 2 including cycling means for repeatedlya. applying the first and second input signals respectively to the firstand second storage means to set their starting levels,

b. then initiating said change of the stored signals in both storagemeans, and

c. after termination of the change of the stored signal in the secondstorage means reapplying the first and second input signals respectivelyto the first and second storage means to initiate another cycle.

1. Analog computing apparatus comprising storage means so adapted thatthe value of a signal in said storage means may change of the functionof time, said storage means having an input by means of which a firstinput signal may be applied to said storage means to determine astarting level for a stored signal therein, comparison means coupled tosaid storage means for comparing said storage signal with a second inputsignal, as the value of the said stored signal changes with time, andproviding a response when the compared signals have a predeterminedrelationship, which will be after a time interval dependent (in a matterdetermined by the stored signal value/time characteristics of saidstorage means) on said first and second input signals, and convertingmeans coupled to said comparison means and operable by said response toproduce a signal related to the said time interval, which signal willthereby also be dependent on said first and second input signals, saidconverting means including second storage means, so adapted that thevalue of a signal in said second storage means may change as a functionof time, and an input to said second storage means by means of which athird input signal may be applied to said second storage means todetermine the starting level of a stored signal therein, said comparisonmeans being coupled to said second storage means and said second storagemeans being operable by said response of said comparison means toterminate the change of the stored signal therein, whereby the resultantsignal then in said second storage means will be dependent on all threeinput signals, said first and second storage means are such that theirstored signals will change exponentially with time, means for providinga first input signal having a predetermined value, said predeterminedrelationship between said second input signal and the stored signal insaid first storage means is equality, said means for providing the inputsignal or signals having a predetermined value provide said signal orsignals having a value equal to the upper limit value of a ''''livezero'''' signal scale on which scaLe the variable input signal orsignals may represent data values, and including means for setting equaldatum levels for the changing stored signals in the two storage means,the datum levels having a value equal to the lower limit value of said''''live zero'''' signal scale.
 2. Analog computing apparatus comprisingstorage means so adapted that the value of a signal in said storagemeans may change of the function of time, said storage means having aninput by means of which a first input signal may be applied to saidstorage means to determine a starting level for a stored signal therein,comparison means coupled to said storage means for comparing saidstorage signal with a second input signal, as the value of the saidstored signal changes with time, and providing a response when thecompared signals have a predetermined relationship, which will be aftera time interval dependent (in a matter determined by the stored signalvalue/time characteristics of said storage means) on said first andsecond input signals, and converting means coupled to said comparisonmeans and operable by said response to produce a signal related to thesaid time interval, which signal will thereby also be dependent on saidfirst and second input signals, said converting means including secondstorage means, so adapted that the value of a signal in said secondstorage means may change as a function of time, and an input to saidsecond storage means by means of which a third input signal may beapplied to said second storage means to determine the starting level ofa stored signal therein, said comparison means being coupled to saidsecond storage means and said second storage means being operable bysaid response of said comparison means to terminate the change of thestored signal therein, whereby the resultant signal then in said secondstorage means will be dependent on all three input signals, said firstand second storage means are such that their stored signals will changeexponentially with time, means for providing a first input signal havinga predetermined value, said predetermined relationship between saidsecond input signal and the stored signal in said first storage means isequality, said means for providing the input signal or signals having apredetermined value provides said signal or signals having a value equalto the upper limit value of a ''''dead zero'''' signal scale on whichscale the variable input signal or signals may represent data values,and comprising means for ensuring that the datum levels for the changingstored signals in the two storage means are zero.
 3. Apparatus accordingto claim 1 including cycling means for repeatedly a. applying the firstand second input signals respectively to the first and second storagemeans to set their starting levels, b. then initiating said change ofthe stored signals in both storage means, and c. after termination ofthe change of the stored signal in the second storage means reapplyingthe first and second input signals respectively to the first and secondstorage means to initiate another cycle.
 4. Apparatus according to claim2 including cycling means for repeatedly a. applying the first andsecond input signals respectively to the first and second storage meansto set their starting levels, b. then initiating said change of thestored signals in both storage means, and c. after termination of thechange of the stored signal in the second storage means reapplying thefirst and second input signals respectively to the first and secondstorage means to initiate another cycle.